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1 industrial temperature range idt5t940 precision clock generator oc-192 applications november 2004 2004 integrated device technology, inc. dsc 6195/27 c idt5t940 industrial temperature range precision clock generator oc-192 applications the idt logo is a registered trademark of integrated device technology, inc. features: ? input frequency: - for sonet non-fec: 19.44mhz, 38.88mhz, 77.76mhz, 155.52mhz, 311.04mhz, or 622.08mhz - for sonet fec: 20.83mhz, 41.66mhz, 83.31mhz, 166.63mhz, 333.26mhz, or 666.52mhz - for 10ge copper: 19.53mhz, 39.06mhz, 78.125mhz, 156.25mhz, 312.5mhz, or 625mhz - for 10ge optical: 20.14mhz, 40.28mhz, 80.56mhz, 161.13mhz, 322.26mhz, or 644.53mhz ? 3-level inputs for feedback divide ratio and output frequency range selection ? 1x, 2x, 4x, 8x, 16x, and 32x outputs on q out ? regenerated input clock or q out /4 on q reg ? lock indicator ? power-down mode ? lvpecl or lvds outputs ? three modes of output frequency range - mode 0: q out range 155.5 - 166.6mhz. q reg is a regenerated version of the input clock. - mode 1: q out range 622 - 666.5mhz. q reg output 155.5-166.6mhz. - mode 2: q out range 622 - 666.5mhz. q reg is a regenerated version of the input clock frequency. ? selectable loop bandwidths ? hitless switchover ? differential lvpecl, lvds, or single-ended lvttl input interface ? 2.375 - 3.465v core and i/o ? available in vfqfpn package description: the idt5t940 generates a high precision fec (forward error cor- rection) or non-fec source clock for sonet/sdh systems as well as a source clock for gigabit ethernet systems. this device also has clock regeneration capability: it creates a "clean" version of the clock input by using the internal oscillator to square the input clock's rising and falling edges and remove jitter. in the event that the main clock input fails, the device automatically locks to a backup reference clock using a hitless switchover mechanism. this device detects loss of valid clkin and leaves the vco of the pll at the last valid frequency while an alternate input refin is selected. if clkin and refin are different frequencies, the multiplication factor will be adjusted to retain the same output frequency. the idt5t940 can act as a translator from a differential lvpecl, lvds, or single-ended lvttl input to lvpecl or lvds outputs. the idt5t940-10 has lvds outputs and the idt5t940-30 has lvpecl outputs. the three modes of output frequency range are controlled by the selmode, which is a 3-level pin. when selmode is high or low, the q out is a multiplied version of the input clock while q reg is a regenerated version of the input clock. when selmode is mid, the q out is a multiplied version of the input clock while q reg is q out /4. the idt5t940 features a selectable loop bandwidth. applications: ? terabit routers ? gigabit ethernet systems ? sonet / sdh systems ? digital cross connects ? optical transceiver modules functional block diagram pll control logic lock, freq. detector clkin refin lock div n div m q reg q out clk/ ref 0 sel mode pd pllbw 1 pllbw 0 input mux clkin refin clk/ ref 1 q reg q out
2 industrial temperature range idt5t940 precision clock generator oc-192 applications pin configuration note: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute- maximum-rated conditions for extended periods may affect device reliability. absolute maximum ratings (1) symbol description max unit v dd power supply voltage ?0.5 to +4.1 v v i input voltage ?0.5 to +4.1 v v o output voltage ?0.5 to v dd +0.5 v t j junction temperature 150 c t stg storage temperature ?65 to +165 c note: 1. capacitance applies to all inputs except clk/ref [1:0] and selmode. capacitance (t a = +25c, f = 1mhz, v in = 0v) parameter description typ. max. unit c in input capacitance 2.5 3 pf c out output capacitance ? ? pf vfqfpn top view gnd clkin clkin gnd refin refin gnd v dd gnd q reg q reg lock gnd v dd v d d c l k / r e f 1 c l k / r e f 0 s e l m o d e v d d p l l b w 0 p l l b w 1 p d v d d g n d q o u t q o u t g n d v d d 1 2 3 4 5 6 7 21 20 19 18 17 16 15 8 9 10 11 12 13 14 28 27 26 25 24 23 22 gnd symbol description min. typ. max. unit t a ambient operating temperature ?40 +25 +85 c v dd power supply voltage 2.375 ? 3.465 v v t termination voltage (lvpecl) ? v dd ? 2 ? v termination voltage (lvds) ? 1.2 ? recommended operating range
3 industrial temperature range idt5t940 precision clock generator oc-192 applications input frequency range clk/ref [1:0] input frequency range h h 19.4mhz - 20.9mhz h m reserved hl 38.8mhz - 41.7mhz m h 77.7mhz - 83.4mhz m m automatic detection ml 155.5mhz - 167mhz lh 311mhz - 334mhz lm reserved ll 622mhz - 667mhz pll bandwidth selection pllbw [1:0] min. max. min. clkin/refin ll 65khz 120khz 19.44mhz lh 250khz 500khz 19.44mhz hl 1mhz 2mhz 38.88mhz h h 4mhz 8mhz 155.52mhz output frequency range selmode q out /q out q reg /q reg unit l 155.5 - 166.6 regenerated clkin/ clkin mhz m 622 - 666.5 155.5 - 166.6 mhz h 622 - 666.5 regenerated clkin/ clkin mhz pin description pin name i/o type description clkin, clkin i adjustable (1) differential or single-ended clock input signal. for differential, lvpecl or lvds supported. if left open-circuited, inputs w ill float to lvttl threshold voltage so that either input may be used as a single-ended input. a capacitor to ground should be connected on the floating input. refin, refin i adjustable (1) differential reference clock input. the reference clock input is used as an input to the pll when clkin/ clkin fails. differential or single-ended clock input signal. for differential, lvpecl or lvds supported. if left open-circuited, inputs will float to lvttl threshold voltage so that either input may be used as a single-ended input. a capacitor to ground should be connected on the floating input. clk/ref [1:0] i 3-level (2) 3 level inputs controlling pll feedback divider ratio. automatic detection is used if both inputs are mid. selmode i 3-level (2) 3 level input to select output frequency range for q out /q out and q reg /q reg (see output frequency range table) pllbw [1:0] i lvttl pll bandwidth select inputs (see pll bandwidth selection table) pd i lvttl power down control. shuts off entire chip when low. q out , q out 0 adjustable (3) differential clock output. lvpecl or lvds outputs. q reg , q reg 0 adjustable (3) regenerated clock output from clkin/ clkin , lvpecl, or lvds outputs. lock 0 lvttl low when pll is locked to clkin, high in all other conditions v dd pwr power supply gnd pwr ground notes: 1. inputs are capable of translating the following interface standards: single-ended 3.3v lvttl levels single-ended 2.5v lvttl levels differential lvpecl levels differential lvds levels 2. 3-level inputs are static inputs and must be tied to v dd or gnd or left floating. 3. outputs can be lvpecl or lvds. lock frequency detector the 5t940 will lock to, and track, a valid clkin signal; lock will be low when this has occurred. if clkin fails, the 5t940 pll will smoothly switch to lock to refin without generating any glitches on the output. the fact that the pll is locked to refin rather than clkin is indicated by a high state on lock . when a valid input is then applied to clkin, the 5t940 will smoothly switch back to locking on clkin, and lock will go low. lock will also switch to high should the frequency of clkin drift close to the limits of the vco tuning range.
4 industrial temperature range idt5t940 precision clock generator oc-192 applications clock input/output configuration description application refin (mhz) ckin (mhz) selmode q reg (mhz) q out (mhz) non-fec 19.44, 38.88, 77.76, 155.52, 311.04, 19.44 low 19.44 155.52 622.08 mid 155.52 622.08 high 19.44 622.08 38.88 low 38.88 155.52 mid 155.52 622.08 high 38.88 622.08 77.76 low 77.76 155.52 mid 155.52 622.08 high 77.76 622.08 155.52 low 155.52 155.52 mid 155.52 622.08 high 155.52 622.08 311.04 low 311.04 155.52 mid 155.52 622.08 high 311.04 622.08 622.08 low 622.08 155.52 mid 155.52 622.08 high 622.08 622.08 fec 20.83, 41.66, 83.31, 166.63, 333.26, 20.83 low 20.83 166.63 666.52 mid 166.63 666.52 high 20.83 666.52 41.66 low 41.66 166.63 mid 166.63 666.52 high 41.66 666.52 83.31 low 83.31 166.63 mid 166.63 666.52 high 83.31 666.52 166.63 low 166.63 166.63 mid 166.63 666.52 high 166.63 666.52 333.26 low 333.26 166.63 mid 166.63 666.52 high 333.26 666.52 666.52 low 666.52 166.63 mid 166.63 666.52 high 666.52 666.52
5 industrial temperature range idt5t940 precision clock generator oc-192 applications clock input/output configuration description (continued) application refin (mhz) ckin (mhz) sel mode q reg (mhz) q out (mhz) 10ge copper 19.53, 39.06, 78.12, 156.25, 312.5, 19.53 low 19.53 156.25 625 mid 156.25 625 high 19.53 625 39.06 low 39.06 156.25 mid 156.25 625 high 39.06 625 78.12 low 78.12 156.25 mid 156.25 625 high 78.12 625 156.25 low 156.25 156.25 mid 156.25 625 high 156.25 625 312.5 low 312.50 156.25 mid 156.25 625 high 312.5 625 625 low 625 156.25 mid 156.25 625 high 625 625 10ge optical 20.14, 40.28, 80.56, 161.13, 322.26, 20.14 low 20.14 161.13 644.53 mid 161.13 644.53 high 20.14 644.53 40.28 low 40.28 161.13 mid 161.13 644.53 high 40.28 644.53 80.56 low 80.56 161.13 mid 161.13 644.53 high 80.56 644.53 161.13 low 161.13 161.13 mid 161.13 644.53 high 161.13 644.53 322.26 low 322.26 161.13 mid 161.13 644.53 high 322.26 644.53 644.53 low 644.53 161.13 mid 161.13 644.53 high 644.53 644.53
6 industrial temperature range idt5t940 precision clock generator oc-192 applications dc electrical characteristics over operating range for lvttl symbol parameter test conditions min. typ. max unit i ih input high current v dd = 3.465v ? ? 1 a i il input low current v dd = 3.465v ? ? 1 v ik clamp diode voltage v dd = 2.375v, i in = -18ma ? - 0.7 - 1.2 v v in dc input voltage - 0.3 ? +3.465 v v ih dc input high 1.7 ? ? v v il dc input low ? ? 0.7 v dc electrical characteristics over operating range for lvpecl (1) symbol parameter test conditions min. typ. max. unit input characteristics i in input current (clkin, refin) v dd = 3.465v -20 ? +20 a v cmr common mode input voltage 1 ? v dd - 0.3 v v dif differential voltage required to toggle input 100 ?? mv output characteristics v oh output voltage high (terminated through 50 ? tied to v dd - 2v) (2) v dd - 1.15 ? v dd - 0.9 v v ol output voltage low (terminated through 50 ? tied to v dd - 2v) (2) v dd - 1.95 ? v dd - 1.61 v v swing peak-to-peak output voltage swing 0.55 ? 0.93 v notes: 1. v dd = 2.375 - 3.645v. 2. not to exceed v dd - 0.05v. power supply characteristics (1,2) symbol parameter test conditions typ. max unit i dd _ pd power supply current v dd = max., pd = gnd, all outputs unloaded ? 50 a ? i dd power supply current per input high v dd = max., v in = 2.375v ? 100 a (lvttl inputs only) i tot total power supply current v dd = max., q out = 622mhz, all outputs unloaded ? 200 ma notes: 1. these power consumption characteristics are for all the valid input interfaces and cover the worst case input and output inte rface combinations. 2. as a general requirement, these parts must be capable of operating at the maximum frequency under a nominal load at a reasona ble operating temperature. that means that these parts must not burn up under extended use in a typical application. note: 1. these inputs are normally wired to v dd , gnd, or left floating. internal termination resistors bias unconnected inputs to v dd /2. if these inputs are switched dynamically after powerup, the function and timing of the outputs may be glitched, and the pll may require additional t aq time before all datasheet limits are achieved. dc electrical characteristics over operating range symbol parameter test conditions min. max unit v ihh input high voltage level (1) 3-level inputs only v dd ? 0.4 ? v v imm input mid voltage level (1) 3-level inputs only v dd /2 ? 0.2 v dd /2 + 0.2 v v ill input low voltage level (1) 3-level inputs only ? 0.4 v v in = v dd high level ? 200 i 3 3-level input dc current v in = v dd /2 mid level ?50 +50 a v in = gnd low level ?200 ?
7 industrial temperature range idt5t940 precision clock generator oc-192 applications input timing requirements symbol parameter min. typ. max. unit ref h input reference clock duty cycle 40 50 60 % f ref input reference clock range 19.44 ? 666.52 m h z ref tol input reference clock frequency tolerance -100 ? 100 ppm f clkin clock in frequency range 19.44 ? 666.52 m h z clkin h clock in duty cycle 40 50 60 % t aq acquisition time from return of valid clkin ? 60 150 us lock tol frequency tolerance for lock -600 450 600 ppm t jit ( tol ) tolerance to input jitter gr-253 sect. 5.6.2.2 symbol parameter min. typ. max. unit selmode = low 155.52 ? 166.63 q out multiplied clock output frequency selmode = mid 155.52 ? 666.52 m h z selmode = high 622.08 ? 666.52 q reg regenerated clock output frequency 19.44 ? 666.52 m h z clkin input clock frequency 19.44 ? 667 m h z t r output rise time lvpecl ? 150 ? ps lvds ? 100 ? t f output fall time lvpecl ? 150 ? ps lvds ? 100 ? t sk skew between q out and q reg ? 10 20 ps pllbw pll bandwidth setting 65 80 120 khz t p jitter transfer peaking ?? 0.1 db t j jitter generation (1) output frequency = 622mhz - 666.5mhz ? 0.3 0.65 ps (rms) (with 50khz to 80mhz band pass filter) output frequency = 155.5mhz - 166.6mhz ? 1 2 t duty output duty cycle 45 ? 55 % ac electrical characteristics over operating range (oc-192) note: 1. all input frequencies and pllbw [1:0] permitted by pll bandwidth selection table. dc electrical characteristics over operating range for lvds symbol parameter test conditions min. typ. max. unit input characteristics i in input current (clkin, refin) v dd = 3.465v -20 ? +20 a v cm common mode input voltage range (1) 0.9 ? v dd - 0.05 v v dif differential voltage required to toggle input 100 ?? mv output characteristics v ot(+) differential output voltage for the true binary state 247 ? 454 mv v ot(-) differential output voltage for the false binary state -247 ? -454 mv ? v ot change in v ot between complementary output states ?? 50 m v v os output common mode voltage (offset voltage) 1.125 1.2 1.375 v ? v os change in v os between complementary output states ?? 50 m v i os outputs short circuit current v out(+) and v out(-) = 0v ? 924ma i osd differential outputs short circuit current v out(+) = v out(-) ? 612ma note: 1. not to exceed v dd - 0.05v.
8 industrial temperature range idt5t940 precision clock generator oc-192 applications symbol parameter min. typ. max. unit selmode = low 155.52 ? 166.63 q out multiplied clock output frequency selmode = mid 155.52 ? 666.52 m h z selmode = high 622.08 ? 666.52 q reg regenerated clock output frequency 19.44 ? 666.52 m h z clkin input clock frequency 19.44 ? 667 m h z t r output rise time lvpecl ? 150 ? ps lvds ? 100 ? t f output fall time lvpecl ? 150 ? ps lvds ? 100 ? t sk skew between q out and q reg ? 10 20 ps pllbw pll bandwidth setting 65 80 120 khz 250 305 500 t p jitter transfer peaking ? 0.05 0.1 db output frequency = 622mhz - 666.5mhz ? 0.1 0.3 t j jitter generation output frequency = 155.5mhz - 166.6mhz ? 0.4 1.5 ps (rms) (with 12khz to 20mhz filter) (1) output frequency = 77.7mhz - 83.4mhz ? 0.5 1.7 t duty output duty cycle 45 ? 55 % ac electrical characteristics over operating range (oc-48) symbol parameter min. typ. max. unit selmode = low 155.52 ? 166.63 q out multiplied clock output frequency selmode = mid 155.52 ? 666.52 m h z selmode = high 622.08 ? 666.52 q reg regenerated clock output frequency 19.44 ? 666.52 m h z clkin input clock frequency 19.44 ? 667 m h z t r output rise time lvpecl ? 150 ? ps lvds ? 100 ? t f output fall time lvpecl ? 150 ? ps lvds ? 100 ? t sk skew between q out and q reg ? 10 20 ps 65 80 120 pllbw pll bandwidth setting 250 305 500 khz 1000 1250 2000 t p jitter transfer peaking ? 0.05 0.1 db output frequency = 155.5mhz - 166.6mhz ? 0.3 1.1 t j jitter generation output frequency = 77.7mhz - 83.4mhz ? 0.4 1.3 ps (rms) (with 3khz to 5mhz filter) (1) output frequency = 19.4mhz - 20.9mhz ? 0.5 1.6 t duty output duty cycle 45 ? 55 % ac electrical characteristics over operating range (oc-12) note: 1. all input frequencies and pllbw [1:0] permitted by pll bandwidth selection table. note: 1. all input frequencies and pllbw [1:0] permitted by pll bandwidth selection table.
9 industrial temperature range idt5t940 precision clock generator oc-192 applications lvds driver a b 50 ? v t test point 50 ? v diff lvpecl driver a 50 ? v dd - 2v 50 ? b v diff 50 ? 50 ? v diff v t a b 50 ? 50 ? v diff v b a b v b = v dd - 2v test conditions test circuit for lvds output characteristics test circuit for lvds input characteristics test circuit for lvpecl output characteristics test circuit for lvpecl input characteristics
10 industrial temperature range idt5t940 precision clock generator oc-192 applications recommended landing pattern nl 28 pin note: all dimensions are in millimeters.
11 industrial temperature range idt5t940 precision clock generator oc-192 applications ordering information idt xxxxx xx x package process device type i 5t940-10 5t940-30 precision clock generator - lvds output precision clock generator - lvpecl output thermally enhanced plastic very fine pitch quad flat no lead package vfqfpn - green nl nlg -40c to +85c (industrial) corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 clockhelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com

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